SX-4 Series General Description

Contents

Proprietary Notice

Documentation Log

Introduction

Chapter 1, Developmental Background

1.1 Developmental Philosophy

1.2 Features of the SX-4 Series

1.2.1 Scalable Parallel Vector Systems

1.2.2 SUPER-UX, an Enhanced UNIX-Based Operating System

1.2.3 Software Development Environment Vector and Parallel Requirements

2.1 SX-4 Series Applications Systems

2.1.1 High Performance Applications Systems

2.2 SUPER-UX Overview

2.3 Hardware Overview

2.3.1 System Configuration

2.3.2 Architecture

2.4 LSI Technology

2.4.1 CMOS LSI

2.4.2 Packaging and Cooling Technologies

2.4.3 Highly Reliable System

3.1 Organization of SUPER-UX

3.2 IOX Software

3.3 Initial System Loader (ISL)

3.4 SUPER-UX Kernel

3.4.1 Basic Kernel Services

3.4.1.1 Memory Management

3.4.1.2 Process Management

3.4.1.3 Execution Management

3.4.1.4 Parallel Processing Services

3.4.2 File Management

3.4.2.1 Organization of the SUPER-UX File System

3.4.2.2 Supercomputing File System (SFS)

3.4.2.3 Hybrid Supercomputing File System (SFS/H)

3.4.2.4 Easy-to-use File System Environment

3.4.2.5 Intelligent I/O Accelerator Subsystem (IAS)

3.4.2.6 SFS and IAS Utilities

3.4.2.7 Network File System (NFS)

3.4.2.8 Tape Library

3.4.2.9 SX-BackStore

3.4.3 Batch Processing

3.4.4 Network Functions

3.4.4.1 Overview

3.4.4.2 Local Area Network (LAN) Connection

3.4.4.3 Wide-Area Network (WAN) Connection

3.4.4.4 Streams

3.4.4.5 Internet Protocol

3.4.4.6 OSI Protocol

3.4.4.7 Network Utilities

3.4.5 Operation Management Services

3.4.6 High Reliability

3.5 SUPER-UX Utilities

3.5.1 Overview

3.5.2 Shell

3.5.3 Basic Commands

3.5.4 BSD Commands

3.5.5 NQS

3.5.6 X-Window

3.5.7 Distributed Computing Environment

3.6 Multi-node Systems

4.1 FORTRAN90/SX

4.1.1 Language Specifications

4.1.2 Automatic Vectorization

4.1.3 Parallelization

4.1.4 Optimization

4.1.5 High-speed Input/Output Features

4.1.6 XMU Array Function

4.2 FORTRAN77/SX

4.2.1 Language Specifications

4.2.2 Automatic Vectorization, Parallelization, and Optimization Features

4.3 C/SX

4.3.1 Overview

4.3.2 Automatic Vectorization Features

4.3.3 Parallelization Features

4.3.4 Optimization Features

4.4 C++ Language

4.5 HPF/SX

4.6 MPI/SX

4.7 Performance Enhancement Support Tools

4.7.1 ANALYZER-P/SX

4.7.2 ANALYZER90/SX

4.7.3 PARALLELIZER/SX

4.7.4 C-ANALYZER/SX

4.8 Development Support Tools

4.9 Debugging Support Tools

4.10 Cross Development Environment

4.11 Conversion Support Tool

5.1 Mathematical Libraries

5.1.1 Advanced Scientific Library ASL/SX

5.1.2 Advanced Scientific Library C Language Interface ASLCINT/SX

5.1.3 Advanced Scientific Library External Memory Extension ASLEME/SX

5.1.4 Mathematical Library MATHLIB/SX

5.2 Graphics Software

5.2.1 Graphical Kernel System (GKS)

5.2.2 Three-Dimensional Graphics System (PHIGS PLUS)

5.2.3 Visual Simulation System (SXview)

5.3 Molecular Science Software

5.3.1 Ab initio Molecular Orbital Calculation System (AMOSS/SX)

5.4 Flow Simulation Software

5.4.1 ThreeDimensional Real-Time Flow Simulation System (-FLOW/SX)

5.5 Third-party Software

6.1 Central Processing Unit

6.1.1 Configuration of Central Processing Unit

6.1.2 Vector Unit

6.1.3 Scalar Unit

6.2 Main Memory Unit

6.3 Extended Memory Unit

6.4 Internode Crossbar Switch

6.5 Input/Output Processor

6.5.1 Input/Output Processor Configuration

6.5.2 Maximum Number of Channels

6.6 Input/Output Multiplexer

6.7 Automatic Operation Controller

6.8 Peripheral Devices

6.8.1 High Speed RAID Disk Subsystem

6.8.2 SCSI Disk Units

6.8.3 Tape Systems

6.8.4 Network Facilities

Index

Figures

1-1 Configuration of a Single-node Model

1-2 Configuration of a Multi-node Model

1-3 Detailed Configuration of the SX-4 Processor

2-1 Features of SUPER-UX

2-2 Configuratoin of a Single-nde System (Maximum Configuration)

2-3 Configuration of an H type (Maximum Configuration)

2-4 Configuratoin of an M type (Maximu Configuration)

2-5 Parallel Processing

2-6 Reducing I/O Processing Time Through the Use of an Extended Memory Unit

2-7 Vectorization Ratio and the Effect of Vectorization

2-8 Various Vector Processing Fucntions

2-9 Effect of Parallel Execution of Vector and Scalar Instructions

2-10 Benefits of a Superscalar Architecture

2-11 Summary of Architecture-driven Performance Improvements

2-12 Basic Data Formats

2-13 Principal Instruction Formats

2-14 Effective Address for a Vector Function

2-15 Effective Address for Scalar Instruction

2-16 Generating an Absolute Address

2-17 LSI

2-18 External View of an LSI Chip

2-19 Bi-CMOS Static RAM

2-20 CPU Card

2-21 MMU Card

3-1 SUPER-UX Software System

3-2 Organization of the SUPER-UX File System

3-3 File Hierarchy

3-4 Configuration of i List and i Node

3-5 Conceptual Diagram of a Virtual Volume

3-6 Virual Volume Cache Configuration

3-7 Parallel Input/Output Service

3-8 Sample Network Configuration Using FDDI

3-9 Example ATM Network

3-10 Example HIPPI Network

3-11 Example Wide Area Network

3-12 Protocols Supported by SUPER-UX

3-13 SUPER-UX API Support

3-14 OSI Architecture

3-15 SUPER-UX Distributed Processing

3-16 SUPER-UX RAS Features

3-17 Source and Destination Redirection

3-18 Sample Batch Request

3-19 Example NQS Configuration

3-20 Example NQS Status Display

3-21 NQS Load Distribution Feature

3-22 X-Windos System Configuration

3-23 DCE Architecture

4-1 Vector Types

4-2 Vector Gathering and Scattering

4-3 Flow of Asynchronous Input/Output

4-4 Processing Flow of XMU Array Function

4-5 Data Distribution in HPF

4-6 HPF Program Example

4-7 Data Distribution in Terms of Nodes

4-8 Data Distribution in Terms of CPUs

4-9 MPI Overview

4-10 Differences in Performance According to Vectorization Ratio

4-11 Relationship Between Vectorization Ratio and Performance Improvement Ratio

4-12 Steps for Performance Improvement by Vectorization

4-13 Example of a Program Structure List Report by ANALYZER-P/SX (Static Analysis)

4-14 Example of Macrotasking Cross Reference List Report by ANALYZER-P/SX (Static Analysis)

4-15 Example of a Summary List Report by ANALYZER-P/SX (Dynamic Analysis)

4-16 Example of a Macrotasking Summary List Report by ANALYZER-P/SX (Dynamic Analysis)

4-17 Example of a Program Unit List Report by ANALYZER-P/SX (Dynamic Analysis)

4-18 Example of a Calling Patch List Report by ANALYZER-P/SX (Dynamic Analysis)

4-19 Example of a Edited Program List Report by ANALYZER-P/SX (Dynamic Analysis)

4-20 Example of a Program Unit Summary List Report by ANALYZER-P/SX

4-21 Example of a Program Unit Detail List Report by ANALYZER-P/SX

4-22 Relationship Between Compilers and Performance Analysis Tools

4-23 PARALLELIZER/SX Display Example

4-24 Summary List Report Example (Execution Time Analysis)

4-25 Function Summary List Report Example (Execution Time Analysis)

4-26 Portion of Sample Report of an Edited Program List (Execution Frequency Analysis)

4-27 Flow of CONVERTER/SX

6-1 Vector Operation Pipelines

6-2 Operation Pipelines and Automatic Chaining

6-3 Array Data and its Placement in Main Storage

6-4 Scalar Unit Configuration

6-5 Effects of Scalar Operatoin Pipelining

6-6 Character of Iteration Loops and Branch Instructions

6-7 Single-node Main Memory Unit Configuration

6-8 Configuration of Extended Memory Unit

6-9 Input/Output Processor Configuration

6-10 Input/Output Processor Configuration by Model Group

6-11 Automatic Operation Controller Configuration

2-1 Specifications for Compact Models

2-2 Specifications for Single-node Models (Representative Models)

2-3 Specifications for Mult-node Models (Representative Models)

2-4 Principal Vector Instructions

4-1 Outline of FORTRAN90/SX Automatic Vectorization

4-2 Outline of Automatic Parallelization

4-3 Basic Conditions for the Automatic Vectorization Features of the C/SX Compiler

4-4 Features for Vectorizing Loops that Do Not Statisfy Basic Conditions

4-5 Features that Improve the Efficiency of Generated Vector Instructions\

4-6 Outline of C/SX Parallelization

4-7 Outline of the Optimization Features of the C/SX Compiler

6-1 Specifications of Main Memory Unit

6-2 Specifications of Extended Memory Unit